1. Field of the Invention
The present invention relates to semiconductor fabrication processes, and more particularly, to a semiconductor fabrication process for fabricating MOS (metal-oxide semiconductor) transistors having anti-punchthrough implant regions formed by the use of phase-shift masks.
2. Description of Prior Art
The advance in semiconductor fabrication technology allows computers and electronic devices to be made more complex in structure to provide powerful performance. With increased consideration of cost and reliability, the demand for ICs with a high packing density of transistors increases. Allowing high packing density on ICs is not a task easily achievable simply by reducing the feature proportions of the circuit layout size because such a change in the feature proportions of the circuit layout size is restricted by the design rule. Moreover, the change in the size of a semiconductor device could also result in a change in its physical characteristics.
In the case of a MOS transistor, its channel length is limited to a certain level of reduction. If the channel length is shorter than that limit, the undesired results of short channel effect and punchthrough occur. A solution to the short channel effect problem is to apply a lightly doped drain (LDD) structure to the MOS transistor; and a solution to the punchthrough problem is to apply anti-punchthrough implantation to the MOS transistor so as to raise the threshold punchthrough voltage therein.
FIGS. 1A-1D, are schematic sectional diagrams depicting the steps involved in a conventional process for fabricating an N-type MOS transistor. Referring to FIG. 1A, in the first step a p-type substrate 200 is prepared, on which a layer of pad oxide 202 and a layer of silicon nitride 204 are successively formed. Next, a lithographic process is performed, in which a photoresist layer 206 is coated on the active regions of the silicon nitride layer 204 and an active mask is then used for etching the exposed silicon nitride. The remaining silicon nitride is then used as a mask for channel stop implant using high-concentration p-type ions.
Referring next to FIG. 1B, in the subsequent step the photoresist layer 206 is removed and the remaining silicon nitride acts as an anti-oxidation mask. The wafer is then subject to heat oxidation treatment to form field oxide regions 212. The silicon nitride layer 204 and the pad oxide layer 202 are then removed. The result is a LOCOS layer.
Referring further to FIG. 1C, after the silicon nitride layer 204 and the pad oxide layer 202 are removed, a thin protective oxidation layer 222 is formed. Next, a threshold adjustment implant region 232 and an anti-punchthrough implant region 234 are formed by using p-type ions such as boron ions. The provision of these two regions 232, 234 allows increase in the concentration of impurities within and below the channel so as to raise the critical voltage and punchthrough voltage in the MOS transistor to desired levels.
Referring finally to FIG. 1D, a gate layer (the anti-punchthrough implant region) 235 and source/drain regions 236 are formed. The gate layer 235 can be polycrystalline silicon or polycide; and the source/drain regions 236 are made in such a way so as to prevent the short channel effect. The involved processes are conventional techniques well known to those skilled in the art of semiconductor fabrication, so the details thereof will not be described herein.
In response to growing demand for higher packing density, it is necessary to shorten the length of the channel in the MOS transistor to less than 0.5 .mu.m. This level of reduction causes the foregoing conventional anti-punchthrough implantation process not to meet current requirements. As shown in FIG. 1D, if the channel length is shorten to less than 0.5 .mu.m, the anti-punchthrough implant region 234 comes in very close proximity to the source/drain regions 236. This causes the source/drain regions 236 to have high junction capacitance, which delays any electrical signal passing therethrough and thus the performance of the MOS transistor is considerably affected.
Accordingly, there exists a need for a MOS transistor fabrication process by which the anti-punchthrough implant region is formed only beneath the channel having a length of less than 0.5 .mu.m and does not overlap with the source/drain regions, so as to significantly reduce the junction capacitance of the source/drain regions for performance enhancement. However, the restrictions of current design rules make such a goal is still difficult to achieve.